Circuitry and algorithms are known for receiving digital diagnostic images from a diagnostic imaging source where the image is received via an interconnecting cable in a "packet" format comprised of image pixels and framing characters on a line by line basis. In particular is the UBMED protocol that specifies signals, and timing relationships between the signals in a "packet" image transfer network. Designed by Siemens Company, this protocol is employed for example in systems such as the General Electric Advantx DX DSA scanner, the Siemens Somatom Plus CT scanner, Philips Gyroscan T5 and T15 MR scanners, and the Resonex RX4000 MR scanner.
Known systems employed to receive images transmitted according to the UBMED protocol, as represented by the KEDI-M1O00 sold by the Eastman Kodak Company, Rochester, NY., operate in a serial, non-concurrent mode, where each data packet of the image is received into a First-in-First-Out (FIFO) memory, processed by a Logic and Control Unit, stored in conventional Random Access Memory (RAM), and then a new packet is requested from the imaging source. This method is inherently slow due to the serial nature of the data processing path, and the need to wait until the entire data packet has been received in the FIFO before local processing can begin. In such a case, the next packet or a repeat of the current packet cannot be requested until the current line has been completely stored in RAM, and all testing for data validation has been completed.
Referring to FIG. 1, an overall view of the system interconnection is shown with the Image Transmitter 110, the Image Receiver 112, and the electrical signals interconnecting these system components. The Image Transmitter 110 can be any image data source equipped with a data transmitter that produces the specified interconnection signals, and transmits the image data on a line by line basis wherein each line consists of framing and data characters as shown in FIG. 2.
Referring to FIG. 2, the data line consists of a start of Message Character 114, a Message Type Character 116, and the Image Data 118, and an end of Line/Image Character 120. The Framing Characters 114, 116, and 120 are differentiated from the image data 118 by the Mode Bit (FIG. 3, 124). Referring to FIG. 3, the Mode Bit 124, when combined with the Data 122, produce the Framing Character Types 126. Referring to FIG. 2, the framing character values may vary from different imaging sources, but the Line Format 114, 116, 118, and 120 remains constant.
The transfer image size is specified in the first line that is transmitted to the receiver by replacing the Data Characters 118, with the image size consisting of a four byte sequence specifying the line size most significant byte, the line size least significant byte, the number of lines most significant byte, and the number of lines least significant byte. Referring to FIG. 4, this information is utilized by a Logic and Control Unit 134 to verify that an image transfer is completed with no missing or extraneous data.
In reference to FIG. 4, an image transfer is initiated by the Logic and Control Unit 134 asserting a DATA REQUEST to the host system. The host system transmitter then responds to the receiver by sending the image size line specifying the image size parameters. The transmitted line is stored in the FIFO 128, and the framing characters are also recorded by the Mode Counter 130. The Mode Counter 130 is loaded with a value of three, and decrements by one each time a Mode Character is received from the host system. Upon recording the third Mode Character, the Mode Counter 130 outputs a EOL signal to the Logic and Control Unit 134, which then negates the DATA REQUEST. Additionally, as each character is received, the parity of the character is checked by the Parity Check Circuit 132, and an error latch is set if the parity does not match the prescribed type.
Upon receiving the EOL signal from the Mode Counter 130, the Logic and Control Unit 134 samples the ERROR signal from the Parity Check Circuit 132. If the ERROR signal is asserted, contents of the FIFO 128 are discarded and the Logic and Control Unit 134 proceeds to order a repeat of the received line by asserting the REPEAT REQUEST signal in conjunction with the DATA REQUEST. This sequence is repeated a predetermined number of times, or until the line is received with no errors.
If the ERROR signal is not asserted, a Mode Evaluator 152 in the Logic and Control Unit 134 proceeds to check the first two characters in the FIFO 128 for proper values, then orders a FIFO (128) reset and a REPEAT REQUEST if the values are not the expected values. If the first two characters are of the expected value, the Logic and Control Unit 134 then initiates a transfer of the data characters in the FIFO 128 to the Image Memory 136 over the System Bus 142, and records the transfer of each character by an increment of the value in a Pixel Done Counter 144 in the Logic and Control Unit 134, which is then compared with the expected line size. The FIFO 128 status is monitored by the Logic and Control Unit 134 by sampling the EMPTY signal produced by the FIFO. Should the FIFO 128 go empty before the Pixel Done Counter 144 in the Logic and Control Unit 134 increments to the line size value that was received in the first "packet" and stored in the Logic and Control 134, an error condition is declared and the Logic and Control Unit 134 will reorder the data line.
When the Pixel Done Counter 144 of the Logic and Control Unit 134 increments to the line size value, the EMPTY signal is sampled to insure that there is still at least one character left in the FIFO 128. Should the EMPTY signal be asserted, the Logic and Control Unit 134 will declare an error condition and reorder the data line if possible, depending on host system timing constraints. If the host system timing constraints do not allow the data "packet" to be reordered, the image transmission is aborted and restarted from the first line. This results in undesirable transmission delays and inefficient use of the data transmission channel. Otherwise, the Logic and Control Unit 134 reads another character from the FIFO 128 and the Mode Evaluator 152 evaluates it for the expected and end-of-line character value. Should the value not be the expected value, an error condition is declared and a reorder of the data line is executed, otherwise the EMPTY signal is checked to insure that no more characters reside in the FIFO 128. Should the EMPTY signal not be asserted, an error condition is declared and a reorder of the data line is executed, otherwise a Line Counter 154 in the Logic and Control Unit 134 increments by one. If the Line Counter 154 in the Logic and Control Unit 134 is equal to the line number value that was received in the first "packet" and stored in the Logic and Control Unit 134, then the image transfer has been completed, otherwise the next data line is requested from the host system, and the process is repeated until the entire image has been received.
It is the object of the present invention to provide an improved digital data transmission system operating according to the UBMED protocol that avoids the shortcomings noted above.